The present invention generally relates to semiconductor manufacturing processes employing photolithography and etching processes to form circuit patterns on a semiconductor wafer, and deals more particularly with an improved mask used to image circuit patterns onto the wafer to achieve uniform features across the entire field of the imaged pattern.
Well known photolithography processes for forming circuit patterns on semiconductor wafers to produce integrated circuits typically employ a mask for imaging complex circuit patterns onto the wafer. The subsequent semiconductor processes used to form integrated circuits (IC""s) typically include chemical and physical film depositions, etching, ion implantation, defusion, annealing or thermal oxidation. Many of these processes require that a pattern of photoresist first be formed on the wafer substrate. The technique for patterning the photoresist is referred to as a photolithography process, which involves first depositing a uniform layer of photoresist onto the substrate, next exposing the photoresist layer to optical or illumination through the mask, and then developing the exposed photoresist layer. The patterned photoresist layer that results from this process corresponds to the pattern on the mask. Depending upon the type of photoresist used, the image is either a positive one or a negative one.
A conventional mask used in a so-called step-and-repeat or xe2x80x9cstepperxe2x80x9d machine, consists of a thin layer of chromium (typically 500 nm) deposited and then patterned on a flat glass or quartz substrate. During the photolithography process, the masked pattern is reduced by a certain factor, for example by a factor of five after it is transferred onto the substrate by a lithographic exposure system forming part of the stepper. This pattern is typically binary i.e. it is either opaque or transparent. In a conventional optical lithography system, the image resolution and the depth of the focus are determined by the wavelength of the illumination light and the numeric aperture of the optics, and not by the mask itself.
Over the last decade, innovations in photolithography have been directed toward improving resolution and alignment accuracy, increasing throughput and reducing defects. As integrated circuit technology advances, the number of layers in an IC has increased, and as a result, the number of photolithographic processes required to fabricate an IC has also increased.
A number of factors have an influence on design limits, circuit performance and defect rate. The minimum image size that can be printed on the surface of a substrate with a specified xe2x80x9cfidelityxe2x80x9d depends primarily on the resolution of the photographic apparatus and resist properties. Other factors, however, such as process-induced fluctuations in pattern dimensions, device reliability and circuit performance play important roles in determining design guidelines. These factors sometimes restrict the patterns to dimensions that are not at the xe2x80x9cphotolithographic limitxe2x80x9d. For example, etching, oxidation and lateral diffusion of dopants can cause the final wafer dimensions to deviate considerably from those defined in a resist; reliability concerns, such as electromigration in metals, may limit the metal width or contact size to dimensions larger than the minimum feature size. Dimensions that must be rigorously controlled during mask inspection and after imaging on the resist to ensure that circuits operated within specifications are called critical dimensions (CD). The imaging process, as well as other factors can cause the average line width that is measured in the resist to be larger or smaller than on the mask. This difference is sometimes referred to as the xe2x80x9cbiasxe2x80x9d. Fluctuations in the imaging process cause variations in the resist dimensions. These latter mentioned variations are referred to as tolerances. To some degree, these variations may be taken into consideration when designing the layout of the circuit pattern.
However, not all process variations can be compensated for by adjustments in the design layout of the circuit pattern. One such process that materially affects CD""s is that of etching of the exposed layer of photoresist. In typical plasma reactors, the etch rate is proportional to the concentration of reactive species which, on average, is determined by the difference of the rates of generation and loss of species. In typical plasma reactors, the main loss mechanism of etchants is their consumption by reaction with the material being etched. Therefore, more reactive neutrals are depleted as the etchable surface area is increased. Since the generation of reactive species is independent of the amount of etchable material present, there is a net loss of reactive species which increases as more etchable substrate is exposed. The result is a decrease in the etch rate as the exposed surface area is increased, a phenomena referred to as xe2x80x9cloading effectxe2x80x9d. Well known formulas defining the relationship between the etch rates and other variables show that there is negligible loading when the exposed area being etched is very small and/or the lifetime of the active species in the absence of etchable material is small. Therefore, loading defects can be reduced by employing plasmas in which the dominant etch loss mechanism is insensitive to the consumption by reaction.
The most serious concern caused by the loading effect is the loss of etchant control when nearing the xe2x80x9cend pointxe2x80x9d of an etching process, i.e. when a desired amount of photoresist has been removed. Ideally, as the termination of an etch process is approached, the etch rate should decrease to allow stopping the process at the correct time and minimizing over-etching. With the loading effect, however, the etchable material is exposed during the end point and the etch rate increases rapidly, so that over-etching is carried out at a higher rate than nominal. This makes line width control extremely difficult, since accelerated etching occurs on clearing.
A microscopic loading effect, in which the etch rate is influenced by the size and density of features, is referred to as microloading. This is the consequence of localized concentrations of gradients of etchant species, which are caused by differing rates of reaction with the patterned surface. For feature sizes below about one micron, and an aspect ratio much greater than one, etching rates are observed to depend on pattern density and aspect ratio. The term xe2x80x9cmicroloadingxe2x80x9d is commonly used in the art to describe its dependence of etch rate on the exposed etchable defined by the pattern.
Loading effect can be either global or localized. Global loading effect is dependent upon the total amount of photoresist being etched. However, localized loading effect is effected by the localized density of circuit features, the relative positions of features and the type of materials being etched, where multiple materials are being etched. In connection with semiconductor manufacturing processes for producing conventional integrated circuits, it has been observed that the etch rate of photoresist defining circuit features along the outer periphery of the imaged pattern, and thus of the mask, tend to etch at a higher rate than the main body or the central area of the wafer. This higher etch rate along the marginal areas of the overall pattern is due to the loading effect caused by the absence of etchable materials immediately outside the borders of the imaged pattern. In other words, circuit features are present up to and sometimes contiguous with the outside borders of the overall imaged pattern, but etchable material is not present outside the border. As the result, there is less overall etchable material around those circuit features being etched at the marginal area of the field, thus causing them to etch at a higher rate. This loading effect along the outer border of the imaged field results in critical dimensions of circuit features along the border which are lesser in quality than those in the main, central field of the image.
The present invention is directed towards achieving overall uniformity of CD""s across the entire area of the imaged pattern.
According to one aspect of the present invention, a method is provided for forming a semiconductor wafer exposure mask having improved pattern uniformity, comprising the steps of forming a main field pattern in a main field on the mask; forming a dummy field pattern in a dummy field area outside of and adjacent to the outer edges of the main field; and, covering the dummy field pattern with a layer of opaque material to prevent the dummy field pattern from being imaged onto the wafer during exposure of the wafer using the mask. The main field and dummy field are preferably formed substantially simultaneously. The method also includes determining the width of the dummy field pattern required to achieve substantially uniform etch rates during etching of the mask. It is also preferable to select a pattern density for the dummy field pattern that is substantially equal to the pattern density of the main field pattern. The dummy field pattern is covered on the mask by depositing an opaque film of material, such as carbon over the dummy pattern on the mask.
According to another aspect of the invention, a mask is provided for use in imaging a pattern onto a semiconductor wafer during a photolithography process. The mask includes a transparent plate, a main field pattern formed on a central area of the plate, a dummy field pattern formed on the plate along the periphery of the main field and an opaque layer of material formed over the dummy layer which blocks the transmission of light, whereby to prevent the dummy features being imaged onto the wafer. The dummy field pattern preferably extends around the entire periphery of the main field pattern, and is defined by a strip of features of substantiality uniform density. The opaque layer of material is preferably selected from the group consisting of carbon, resin and metal. The size of the dummy pattern is generally between 20% and 30% of the size of the main field pattern.
Accordingly, it is the primary object of the present invention to provide a method of forming circuit patterns on a semiconductor wafer having uniform, critical feature dimensions over the entire field of pattern imaged onto the wafer.
Another object of the invention is to provide a method as described above which eliminates loading effect of the etch rate of circuit features along the outer periphery of the circuit pattern formed on the mask.
Another object of the invention is to provide a method as mentioned above which eliminates the etch loading effect through a simple modification of the imaging mask.
A further object of the present invention is to provide a method as described above which can be carried out using conventional manufacturing techniques.
These, and further objects and advantages of the present invention will be made clear or will become apparent during the course of the following description of a preferred embodiment of the invention.